In the fabrication of integrated circuit (IC) interconnect structures, conductive surfaces, such as copper surfaces or cobalt surfaces, formed at the bottom of a via are typically contaminated with etching byproducts and residues formed during via opening and subsequent metal hard mask removal. While large sized particles may be removed by a subsequent dry clean process, the atomic level contamination from etching related elements such as oxygen, fluorine, and carbon or from oxidation due to air exposure on the conductive interconnect surface cannot be removed by a dry clean process.
Typically, the fluorine, oxygen, and carbon contamination can be removed through wet clean methods. However, the inventors have observed that these techniques are not useful for newer back end of the line (BEOL) processes due to compatibility issues with low-k dielectrics as well as recent tighter requirements on low-k damage (e.g., carbon depletion issues). A thermal or mild dry clean is typically used for post via etching to improve electrical performance through a more gentle process.
Accordingly, the inventors have developed improved techniques to reduce the conductive interconnect surface.